1. Field of the Invention
The present invention relates to a via structure of a semiconductor integrated circuit.
2. Description of the Related Art
In a semiconductor integrated circuit in which interconnect layers are multi-layered, a via is adopted to electrically connect a lower-side interconnect and an upper-side interconnect that intersect mutually (See, for example, Jpn. Pat. Appln. KOKAI Publication No. 2004-63667).
One via is commonly provided at a point of intersection of a lower-side interconnect and an upper-side interconnect, but in recent years, two vias are sometimes provided at a point of intersection for the purpose of reducing interconnect resistance and improving manufacturing yields.
Particularly in a semiconductor integrated circuit whose devices are more microscopic, providing two vias at a point of intersection of a lower-side interconnect and an upper-side interconnect is becoming almost a requirement.
This is because interconnect resistance tends to increase and via defects are more likely to be caused as devices become more microscopic. If one via among many vias in a semiconductor integrated circuit becomes defective, the semiconductor integrated circuit itself will be defective so that manufacturing yields cannot be improved.
However, increasing the number of vias provided at a point of intersection of a lower-side interconnect and an upper-side interconnect from one to two means simultaneously increasing a via area at the point of intersection.
That is, to the extent of an increased via area, the number of interconnect pathways of a lower-side interconnect or an upper-side interconnect is reduced, constituting a hindrance to layout of a semiconductor integrated circuit.